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78M6631 Data Sheet
DS_6631_056
1.6
80515 MPU Core
The 78M6631 includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one
clock cycle. The 80515 architecture eliminates redundant bus states and implements parallel execution of
fetch and execution phases. Normally, a machine cycle is aligned with a memory fetch, therefore, most of
the 1-byte instructions are performed in a single machine cycle (MPU clock cycle). This leads to an 8x
average performance improvement (in terms of MIPS) over the Intel 8051 device running at the same clock
frequency .
1.6.1 SFRs
Several custom Special Function Registers (SFR) are implemented in the 78M6631’s 80515 MPU. Refer
to the 78M6631 Programmer’s Reference Manual for more information regarding the mapping of
functionality to specific SFR and IORAM addresses.
1.7
RAM
The CE and MPU share a single, general purpose 4KB RAM (also referred to as XRAM) for data. The
XRAM is natively accessible as 32-bit words from the CE and on 8-bit boundaries from the CPU. The
XRAM is accessed by the CPU through addresses 0x0000 to 0x0FFF.
1.8
IORAM
The MPU accesses most of its external input and output functionality as well as programmable
functionality through memory mapped IO (IORAM). The IORAM is accessed by the CPU as data
addresses 0x2000 to 0x20FF.
1.9
Flash
The 78M6631 includes 128 KB of on-chip flash memory. For read/write access from the CPU, the flash is
broken into four 32 KB banks that are managed by SFR settings. For erasing of the flash memory from
the CPU, the flash is segmented into individual 1024-byte pages and also controlled by SFR settings.
1.9.1 Program Security
The 78M6631 has functionality to guarantee the security of the user’s MPU and CE program code. When
enabled, the security feature limits the ICE to global flash erase operations only. All other ICE operations
are blocked. Security is enabled by MPU code that is executed in a pre-boot interval before the primary
boot sequence begins. Once security is enabled, the only way to disable it is to perform a global erase of
the flash, followed by a chip reset.
10
Rev 2
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